Modern digital circuits, whether implemented in integrated circuits (IC) or in discrete form, often utilize latches to synchronize propagation of data signals. One type of latch, referred to as a level-sensitive latch, provides an output signal having a state that depends upon the activity of the dock signal that is present at a dock input node. In particular, the logic value of the output signal of the level-sensitive latch reflects the logic value of the signal at the input node during a portion of the input dock cycle. In this phase of operation, the latch passes a logic value present at its input node directly to its output node. A latch operating in this phase may be referred to as being transparent. In a second phase of operation, the level-sensitive latch maintains the output signal at a fixed logic value during the remaining portion of the input clock cycle, regardless of the logic value present at the input node. A latch operating in the second phase may be referred to as being latched or held.
Another type of latch, referred to as a flip-flop or edge-triggered latch, is configured to set and hold an output signal to a logic value present at an input node during an edge of a clock signal provided to a clock input node. One implementation of a flip-flop includes a combination of two level-sensitive latches. The first level-sensitive latch, i.e., the master stage, is transparent during a first phase of the input clock, while the second level-sensitive latch, i.e., the slave stage, is transparent during a second phase of the input clock. The combined behavior is such that the input data is captured and passed to the output node only when the clock signal exhibits a low-to-high logic transition. The value of the output signal is maintained until the next low-to-high transition of the clock signal. Conversely, the configuration of the two level-sensitive latches may be altered to capture input data during a high-to-low logic transition of the clock signal.